1. Field of the Invention
Embodiments of the present invention relate generally to memory systems and memory modules. More particularly, embodiments of the invention relate to semiconductor devices comprising a stacked arrangement of integrated circuits (ICs), memory modules incorporating such semiconductor devices, and memory systems incorporating such memory modules.
2. Description of the Related Art
Memory modules have long been used to physically and operationally group semiconductor devices for efficient use within memory systems. Conventional host systems such as servers and personal computers (PCs) routinely incorporate memory systems including memory modules of various configurations. Individual memory modules are typically implemented on a small printed circuit board (PCB) (e.g., a daughterboard) adapted for mechanical and electrical connection with a larger PCB (e.g., a motherboard) via a corresponding slot connector.
FIG. 1 illustrates a conventional memory system comprising an arrangement of memory modules (MM0 through MMn) connected on a motherboard 10 with a corresponding chipset 12. The term “chipset” is used to denote a collection of conventionally understood circuitry adapted to provide power, clock, control, address, and/or data signals to the associated memory modules. This circuitry may be implemented in a single semiconductor package (i.e., a “chip”) or in a family of related chips. As is conventionally understood, the various circuitry in a chipset may take many different forms. A chipset may include, for example, power signal generating circuit(s), a memory controller, a bus re-drive circuit, a phase-lock or delay-lock loop circuit, and/or a clock circuit or clock buffer. At a minimum, however, the term chipset as used throughout this description subsumes circuitry adapted to provide at least one clock signal (CLK) and at least first and second power signals (e.g., Vcc and Vss) to the memory modules.
In the illustrated example of FIG. 1, each memory module is populated with a plurality of semiconductor devices. Semiconductor memory devices, such as DRAMs, are most typically mounted on conventional memory modules, but any synchronous or non-synchronous memory device, and/or non-memory semiconductor device(s) may be mounted on a memory module.
An exemplary and conventional memory module is further illustrated in FIG. 2. The memory module generally comprises a PCB 20 mounting a plurality of semiconductor devices 22 using conventional techniques. As noted above, the semiconductor devices 22 may take one or more conventional forms, but generally include at least one memory device, such as a DRAM, SRAM, and/or SDRAM. A plurality of conductive tabs 24 are typically formed on at least one edge of PCB 20. Tabs 24 are adapted to mechanically connect PCB 20 with a slot connector provided on a motherboard. Tabs 24 are also adapted to provide a connection path by which electrical signals are communicated to/from motherboard components (e.g., the chipset) and components on memory module PCB 20.
Various electrical signals (e.g., data, control/address, power, and/or clock) are communicated from tabs 24 to the plurality of semiconductor devices 22 via numerous signal lines formed on PCB 20. The numerous, very thin, and often geometrically complex signal lines are not shown in FIG. 2 for the sake of clarity. Suffice it to say that these signal lines generally fill much, if not all, of the space (i.e., surface area) practically available on PCB 20 outside of the space allocated to semiconductor devices 22, tabs 24, and certain conventionally understood “peripheral circuits” 23 and 26. There are many different kinds of peripheral circuits, including (e.g.,) Serial Presence Detection (SPD) registers, clock circuits—including PLL and DLL circuits, power capacitors, signal line termination circuits, control/address signal registers, etc.
The past and future expected evolution of semiconductor memory devices may be summarized in one aspect by a statement that semiconductor memory devices have and will continue to store/communicate more data at higher speeds with each succeeding generation. As a result of this truism, an increasing number of signal lines, most carrying signals at faster and faster data rates, are generally required to connect with semiconductor devices mounted on a memory module. Common sense dictates that as the number and layout complexity of signal lines connecting tabs 24 with semiconductor devices 22 increase, the relatively fixed surface area provided by PCB 20 will become increasingly scarce.
The use semiconductor devices comprising an arrangement of stacked integrated circuits (ICs) (hereafter generically referred to as “stacked semiconductor devices”) is one conventional response to the increasing scarcity of available surface area on memory module PCBs. Stated in other terms, the use of stacked semiconductor devices is one approach to greatly increase the number of available semiconductor devices on a memory module without requiring a material expansion in the size of the PCB mounting the semiconductor devices. This advantage is particularly critical in applications where the size of the PCB implementing the memory module is fixed by an applicable design standard or a legacy compatibility requirement, but the performance expectations (e.g., data bandwidth) for the memory module must nonetheless increase.
FIG. 3 generally illustrates a conventional stacked semiconductor device. A board on chip (BOC) packaging technique is shown in the illustrated example of FIG. 3. However, the discussion that follows might readily be applicable to other chip scale packaging (CSP) techniques including as examples, Ball Grid Array (BGA), Lead on Chip (LOC), through-hole stacked packages, etc.
The stacked semiconductor device of FIG. 3 comprises a first semiconductor package 31 mounted on PCB 20 and a second semiconductor package 32 mounted on first semiconductor package 31. (Additional semiconductor packages may of course be stacked on the illustrated example, but the considerations discussed hereafter are not materially altered by a designer's choice of stacking height).
First semiconductor package 31 comprises a semiconductor chip 31a mounted on a substrate 31b. Bonding pads 31c on semiconductor chip 31a are connected to bonding pads 31d on substrate 31b by metal wires which are encapsulated in a protective encapsulation material 31e. One or both primary surfaces of substrate 31b may comprise electrical signal lines (not shown) implemented by conductive patterns formed using conventional techniques. These signal lines rout the various electrical signals described above to/from semiconductor chip 31a. Accordingly, the conductive patterns variously connect ball lands (e.g., 31f and 31g) formed on substrate 31b. Solder balls 33 connect, for example, ball lands 31f on substrate 31b with corresponding ball lands formed on PCB 20. One or more conductive via(s) 34 formed through substrate 31b may be used to connect respective ball lands (such as e.g., 31f and 31g) and/or conductive patterns formed on opposite sides of substrate 31b. 
First and second power signals are provided to semiconductor chip 31a from PCB 20 through power capacitors type peripheral circuits 35 mounted on PCB 20. For example, a first power signal (e.g., Vss) may be provided to semiconductor chip 31a from a signal line or circuit component on PCB 20 through power capacitor 35 and a designated ball land formed on PCB 20. A corresponding solder ball 33 then conducts the first power signal upwards (in the context of the illustrated example) to a corresponding ball land 31f formed on substrate 31b. From this point, the first power signal may be transmitted via a conductive pattern formed on substrate 31b to a designated contact pad 31d through a connecting metal wire to a corresponding bonding pad 31c associated with the semiconductor chip 31a. 
The first power signal may also be conducted from ball land 31f through conductive via 34 to a corresponding ball land 31g. From ball land 31g, the first power signal may be conducted upwards to the second semiconductor package 32 mounted on first semiconductor package 31 through an analogous ball land and solder ball structure. In this manner or an analogous manner, as dictated by the specific stacking technology used to implement the stacked semiconductor device, the first and second power signals, as well as various clock signals and/or control/address/data signals, may be connected from PCB 20 to each semiconductor package in the stacked semiconductor device.
Power capacitors 35 mounted on PCB 20 are conventionally required in order to reduce or remove noise on the respective power signals. Power signal noise tends to increase with the use of higher frequency data signals carried on densely proximate integrated signal lines. Yet, as previously noted these two conditions necessarily arise from the increasing data bandwidth requirements placed on contemporary memory modules.
At some point in nearly all memory module designs, the noise effect of high frequency data signals on numerous, narrow, closely spaced signal lines becomes overwhelming. This is particularly true of DC power signal lines which are notorious for “picking up” high frequency noise from nearby signal lines. Noisy power signals have a well documented history of corrupting data circuit operations within semiconductor memory devices. Accordingly, nearly all power signals applied to semiconductor memory devices mounted on a memory module are provided through a power capacitor.
Power capacitors are a well known, inexpensive and effective mechanism adapted to remove AC noise from DC power signals. Thus, power capacitors are routinely provided as one type of peripheral circuit 23 on conventional memory modules. (See, FIG. 2)
High frequency signal coupling into power signals is not the only type of noise problem that must be addressed in contemporary memory module designs. As the transmission frequency of control/address/data signals communicated to/from semiconductor devices on memory modules increases, the hazard of signal reflections (i.e., another type of noise) on the signals lines also increases. Signal reflections may occur, for example, when signal line impedance(s) are different from the impedance of the signal transmission source. This well understood problem may be addressed by the use of impedance matching termination resistors on the signal lines. Here again, signal line termination resistors are often provided as another type of peripheral circuit 23 on conventional memory modules. (See, FIG. 2).
FIG. 4 further illustrates the conventional reality that many signal lines communicating high frequency data signals connected to/from semiconductor memory devices on a memory module require impedance matched termination in order to reduce or eliminate noisy signal reflections. In FIG. 4, one or more signal lines, generically indicated as I/O bus 40, are respectively connected to the semiconductor memory devices and then terminate at a termination register comprising a termination resistor (Rterm) connected to a termination voltage (Vterm). Conventionally, a termination register, comprising one or more well understood resistive circuits, is typically formed on memory module PCB 20, like the power capacitors 35 shown in FIG. 3.
Unfortunately, the size of power capacitors and the size of termination registers conventionally formed on memory module PCBs are increasing with demands for greater signal line counts and higher operating frequencies. At the same time, signal line routing on the primary surface(s) of the memory module PCB is becoming increasingly restricted. Additionally, the risk of damage to power capacitors and termination registers mounted on the memory module PCB by external mechanical impact is unacceptable high, because, by their very nature, memory modules are intended to be handled by manufacturing personnel during a host device assembly or retrofit.
In sum, despite their effective use within memory module designs, power capacitors and terminations registers have an unfortunate tendency to occupy a disproportionate share of the scarce surface area available on a PCB implementing a memory module. Yet, the recognition of an increasing requirement to condition (e.g., reduce noise) signals applied to semiconductor devices in a stacked semiconductor is not a new one. Despite the apparent drawbacks, the use of PCB mounted power capacitors remains almost universal.
Some previous attempts have been made to provide power capacitors within the structure of a stacked semiconductor device, rather than placing them on the memory module PCB. Consider, for example, U.S. Pat. No. 6,809,421 in which an intermediate substrate is provided between stacked semiconductor packages. The intermediate substrate comprises internally formed, extended signal leads. The extended signal leads are implemented to provide a distributed capacitive effect on power signals connected to the leads. Unfortunately, this approach requires a specially constructed intermediate substrate, and provides only general remedial conditioning of the power signals through the use of a distributed capacitive effect.